The construction of ultra-wideband (UWB) radios, including software defined radios (SDRs) and cognitive radios (CRs), is typically based on two design goals. First, an analog-to-digital converter (ADC) is preferably placed as near the antenna as possible in the chain of radio's frequency (RF) front-end components. Second, the resulting samples are preferably processed on a programmable microprocessor or signal processor. To satisfy these goals, analog components are typically replaced by digital building blocks in radio receivers to lessen circuitry effort (chip size, power consumption, etc.) in the analog domain. Furthermore, additional digital signal processing (DSP) is typically employed to remove spurious effect of the sub-optimum analog front-end.
For analog receivers as shown in FIG. 1, an IQ-imbalance—where I is the in-phase component and Q is the quadrature component of a signal—can be a serious issue that can degrade the receiver's performance. The IQ-imbalance typically occurs due to amplitude and phase impairments between the local oscillator paths and due to mismatches between the respective IQ-branches after the analog down conversion. Such an IQ-imbalance may cause cross talk between in-phase and quadrature (I/Q) components. This, in turn, can cause coupling between the many narrowband channels, creating so-called “ghosts” or “images”. To achieve an imbalance related spectral image 40 dB below a desired spectral term, each imbalance term must be less than 1% of the desired term. It is difficult to sustain, over time and temperature, gain and phase balance of analog components to better than 1%.
Accordingly, IQ balancing typically involves a complex conversion process in the DSP domain. Filter bank techniques, especially a polyphase fast Fourier Transform (Polyphase FFT or “PFFT”) filter bank, have been successfully used in UWB receivers for this purpose. In these receivers, as shown in FIG. 2, the conversion from analog to digital (or digital to analog) occurs at IF rather than at baseband. Therefore, the down conversion of the separated channels is performed by a set of digital down converters and digital low pass filters. Such DSP based complex down conversion does not introduce significant imbalance related spectral terms because the digital process can realize arbitrarily small levels of imbalance by controlling the number of bits involved in the arithmetic operations. Precision of coefficients used in the filtering process sets an upper bound to spectral artifact levels at −5 dB/bit so that 12-bit arithmetic can achieve image level below −60 dB, or −60 dBs/12 bits.
Digital filter bank techniques, including the PFFT filter bank 300 (as diagrammatically shown in FIG. 3A and with a filter bank spectrum is depicted by FIG. 3B) with sampling frequency 303 of fs Hz, are key techniques utilized in UWB receivers for digital complex conversion process to move analog to digital conversion (ADC) from baseband to IF. As shown in FIG. 3A, one or more input signal(s) 301 may be sampled at a sampling frequency 303 by an ADC 302 to output a sampled signal 304. The sampled signal 304 is then typically downcoverted by one or more downconverters 305. In some cases, the one or more downconverters 305 utilize a downconverter sampling frequency of fs/M. In each channel, the samples after downconversion by correspondent downconverter 305 can be filtered by correspondent subband filter 306. The filtered signals can be sent to M point Inverse Discrete Fourier Transform (IDFT) 308 to produce the output signals of yi(m) 310 for each channel.
Typically, a PFFT filter bank can only be applied in IF for IF down conversion. As shown in FIG. 4, the ADC 302 of FIG. 3A typically includes two building blocks: (1) a sample and hold (SH) unit 404 and a (2) quantizer unit 406.
The ADC 302 of the PFFT filter bank 300 as depicted includes a sample and hold (SH) unit and a quantizer. The SH unit 404 receives input signal X(t) 402 and samples it at a sampling frequency 403 of fs for outputting a signal X(n) 405 to the quantizer 406. The quantizer 406 samples the signal X(n) 405 at a sampling frequency 407, which is the same sampling frequency as the SH sampling frequency fs, and outputs signal X(m) to one or more downconverters 410. In each channel, the samples after downconversion by the corresponding downconverter 410 can be filtered by the corresponding subband filter 412. The filtered signals can be sent to M point IDFT 414 to produce the output signals of yi(m) 416 for each channel. The downconverters 410 typically downconvert at a frequency fs/M, where M is a downconverting decimation factor. The downconverted signals 412 are then converted by an M point inverse discrete Fourier transform apparatus 414 into one or more digital baseband channels 416.
Currently, the dynamic range and conversion speed of the ADC 302 becomes a limiting factor in the application of the architecture of receiver shown in FIG. 2. As discussed previously, the dynamic range of the ADC 302 converter is determined by the number of bits in the converter, with each bit contributing 5 dB. To achieve image levels below −60 dB, at least 12-bit resolution or dynamic range is required for the ADC 302. Additionally, the Nyquist criterion establishes the minimum sample rate to obtain alias free representation of the sampled signal. Under current techniques, with 12-bit dynamic range, the conversion speed of the ADC 302 is about 1 GHz, limiting the maximal signal bandwidth that the filter bank can work with to less than 500 MHz. For more than 8 bit resolution, the bandwidth for current PFFT is less than 500 MHz due to the maximal sampling frequency is less than 1 GHz. Due to these limitations, the filter bank techniques are restricted to IF digital conversion with signal bandwidth less than 500 MHz, let alone be applied to RF for RF digital conversion.